Computing devices typically comprise a processor, memory, and a memory controller to provide the processor as well as other components of the computing device with access to the memory. The performance of such computing devices is strongly influenced by the memory latency of the computing device. In general, the “memory read latency” is the length of time between when the processor requests the memory controller to retrieve data from the memory and when the memory controller provides the processor with the requested data. Similarly, the “memory write latency” is generally the length of time between when the processor requests the memory controller to write data to the memory and when the memory controller indicates to the processor that the data has been or will be written to the memory.
To reduce the effect of memory latency on the computing device, memory controllers typically buffer write transactions of the processor and later write the data of the transaction to memory at a more appropriate time. As far as the processor is concerned, the write transaction is complete once buffered by the memory controller. The processor, therefore, may continue without waiting for the data of the write transaction to be actually written to memory. Conversely, read transactions are not complete from the standpoint of the processor until the data is read from memory and returned to the processor. Accordingly, performance of a computing device is typically more dependent upon read latency than write latency.
Moreover, memory latency is influenced by the proportion of page-hit, page-miss, and page-empty transactions encountered. Computing devices typical comprise hierarchal memory arrangements in which memory is arranged in channels, ranks, banks, pages, and columns. In particular, each channel may comprise one or more ranks, each rank may comprise one or more banks, and each bank may comprise one or more pages. Further, each page may comprise one or more columns. When accessing memory, the memory controller typically opens a page of the memory and then accesses one or more columns of the opened page. For a page-hit access, the memory controller may leave a page open after accessing a column of the page for a previous memory request and may access a different column of the open page. For a page-miss access, the memory controller may close an open page of a bank, may open another page of the same bank, and may access a column of the newly opened page. A page-miss access generally has about three times the latency as a page-hit access. For a page-empty access, the memory controller may open a closed page of a bank, and may access a column of the newly opened page for the memory transaction. A page-empty access generally has about twice the latency as a page-hit access.